| 摘要 |
A configurable self-test circuit for a RAM (102) embedded in an integrated circuit chip comprises an incrementable address register (404), a configurable control circuit (406), a write register (412) and a scanpath (402). The address register stores the current RAM address to be accessed and is adapted to automatically increment the RAM address by an address increment upon receiving an increment signal. The configurable control circuit has a normal operation mode and three test modes wherein all writes, all reads or alternating writes and reads are performed. The write register stores data patterns which are to be written to the RAM under test. The signature generator receives data read from the RAM and produces a unique signature in response thereto. A scanpath through the address register, control circuit, write register and signature generator allows test vectors to be serially shifted in and test data to be shifted out of these devices. A full functional test is performed on the RAM. A special test checks the functioning of the pull-up FETs in each RAM cell. <IMAGE> |
