发明名称 I/O bus to system interface
摘要 An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurality of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.
申请公布号 US5261057(A) 申请公布日期 1993.11.09
申请号 US19920912052 申请日期 1992.07.07
申请人 WANG LABORATORIES, INC. 发明人 COYLE, RICHARD W.;CHAO, ZENJA;BERG, THOMAS B.
分类号 G06F13/12;G06F13/40;(IPC1-7):G06F3/00;G06F13/00 主分类号 G06F13/12
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