| 摘要 |
PURPOSE:To reduce the aspect ratio of contact between an external wiring and source and drain regions, by extending the source and drain regions of a transistor to the top of a gate electrode or the top of an adjacent field oxide film and connecting the source and drain regions to the external wiring. CONSTITUTION:An n<-> region 207 into which phosphorus ions are implanted and an n<+> region 209 into which arsenic ions are implanted are formed on a p-type silicon substrate 201. Next, after CVD oxide films 208 and 210 are etched back and removed using a photoresist as a mask until the semiconductor substrate 201 is exposed, a polycrystalline silicon film and a high-melting metal film are deposited and the surfaces of the polycrystalline silicon film and an active region are changed into a silicide film by a rapid heating treatment. Then, the unaltered high-melting metal film is removed, and a silicide region 214 extended to the tops of a field oxide film 202 and a gate electrode 205 is formed. Finally, a contact hole 216 and a top wiring 217 are formed on the top. |
