| 摘要 |
PURPOSE:To easily design a RAM whose position of a data input/output port is different by arranging the word line of a CMOS gate array where plural basic cell stages adjacent in a Y direction have the symmetrical basic stage to an X axis in an X direction, and arranging a bit line in the Y direction. CONSTITUTION:The line 32a between the word lines 32a, 32b is selected and when the line 32a becomes 'H', NMOSTrs 31i, 31j, 31m and 31n whose gates are connected to the line 32a are turned on. The contacts (a) and (b) of a data hold loop constituting a memory cell are connected to the lines 33a, 33b respectively and the contacts ne and nf are connected to the bit lines 33c, 33d respectively. Further, the other word line 32b is 'L' and the NM0STrs 31k, 311, 31p are turned off, and the bit lines 33b, 33c and the contacts nc, nd of the data hold loop, and the lines 33d, 33e and the contacts ng, nh are in a non- contact state respectively. When the word line 32a is raised, the lines 33a-33c become the potential of the contacts na-nf respectively. Since the contacts na and nb, ne and nf are in a complementary relation, by receiving the potential difference by an amplifier, data is read. |
