发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To realize an operation for executing a function output corresponding to the result of addition at a high speed by inputting the result of shifting an output of a decoder by a specific portion by a specific barrel shifter to a memory array part. CONSTITUTION:A decoder 21 decodes first input data 24. In accordance with 00, 01, 10 and 11 being input data binary number expressions of 2 bits, '1' is outputted to four pieces of first - fourth outputs of the decoder, and '0' is outputted to others. These outputs are inputted to a barrel shifter 22, and only a value of second input data 25 is shifted downward. That is, in accordance with 00, 01, 10 and 11 being binary number expressions of second input data of 2 bits, 0-3 bits are shifted downward. In 7 bits of output data of the barrel shifter 22, input data of 4 bits of the barrel shifter is shifted and data of 3 bits outputs '0'. In such a state, '1' is outputted to a position in which values of first and second input data are added, and its result is inputted to a memory array and a function value is read out.
申请公布号 JPH05289852(A) 申请公布日期 1993.11.05
申请号 JP19920090545 申请日期 1992.04.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TOYOKURA MAKI
分类号 G06F7/00;G06F5/01;G06F7/544;G06F7/76 主分类号 G06F7/00
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