| 摘要 |
PURPOSE:To increase the processing speed by connecting the output of a computing element corresponding to an arithmetic instruction to be first executed to the input of a computing element, which corresponds to an arithmetic instruction to be executed later, and the output bus of store data. CONSTITUTION:The arithmetic instruction to be first executed is latched in an instruction register inst1, and data required for execution of this instruction is read out from a register file REG and is operated by a computing element ALU1. When this result is used to execute the arithmetic instruction which is latched in an instruction register inst2 and should be executed later, the output of the computing element AL1 is inputted to a computing element ALU2 through selectors sl7 and sl8, and the operation is completed in the same cycle. When the execution result of the arithmetic instruction in the computing element ALU1 is outputted as store data, the output of the computing element ALU1 is outputted through a selector sl9. Thus, store data is outputted the same cycle as the arithmetic instruction in the computing element ALU1. |
