| 摘要 |
<p>PURPOSE:To provide the reset signal synchronizing circuit being effective and simple for retaining safely the contents of data, even when a reset signal is inputted at an arbitrary time point. CONSTITUTION:In a circuit 10 provided in an input line for inputting a reset signal to a CPU 20, this circuit 10 is provided with a detecting means 11 for detecting the reset signal and an access signal. Also, this circuit is provided with an output means 12 for outputting a reset output signal 6 corresponding to an input 1 of this reset signal to the CPU 20. Moreover, in these means, a means for delaying an output of the reset output signal 6, when an access operation is being executed, and outputting the reset output signal 6 by synchronizing with a timing of finishing the access operation is provided.</p> |
