| 摘要 |
PURPOSE:To provide a semiconductor storage device with a bit line load circuit that has a superior symmetric property in performance by arranging a pair of transistors such that parasitic resistances resulting from ion implantation occur in electrodes of the pair of transistors which are of the same circuit type. CONSTITUTION:If a current flows to a transistor T1 when a memory cell drive transistor is conducted, a voltage between a gate and a source of bit line load transistors T1 and T2 becomes either a potential between VDD and a bit line BL or between VDD and BLB. Hence, no difference due to a logic state of stored information arises in the amplitude of a signal to be inputted to the pair of bit lines BL and BLB. Therefore, the asymmetrical property of a circuit which is a problem in a conventional device becomes improved. For this reason, a sense amplifier, a bit line equalizer circuit or the like, and other circuits associated with a bit line become easy to design. |
