| 摘要 |
PURPOSE:To more shorten the time for phase pull-in setting the PLL circuit generating internal clocks phase locked to external clocks. CONSTITUTION:This circuit is provided with a first PLL control system 10 equipped with a first voltage controlled oscillator (VCO) 13 and a first sweep control means 15 on one hand and provided with a second PLL control 'system 20 equipped with a second VCO 23 similarly constituted and a second sweep control means 25 on the other hand, and voltage control signals to periodically sweep the inside of mutually different controlled voltage ranges are impressed to the respective VCOs 13 and 23 during unsynchronizing. After an external clock f0 is inputted, it is defined as an internal clock f1 to be outputted to the output of the VCO belonging to the system for which synchronism is detected first. |
