| 摘要 |
PURPOSE:To provide the PLL circuit device which can stablize the frequency of a synchronizing clock signal outputted from a voltage controlled oscillation(VCO) circuit even when the input of a reference clock signal is interrupted. CONSTITUTION:This device is provided with a VCO circuit, a frequency divider circuit to input the reference clock signal for this VCO circuit, a frequency detection circuit to input an output of this frequency divider circuit and an output of the VCO circuit and to output the frequency difference as a frequency comparing signal, a counter circuit to input this frequency comparing signal and the synchronizing clock signal, to decide the duty of the output signal corresponding to the frequency difference and to set the level of the controlled voltage, and a filter circuit to convert the output of this counter circuit to a DC signal, and the counter circuit is provided with a duty change stop function to stop the duty change of the output signal when the input of the reference clock signal is interrupted. |
