| 摘要 |
<p>PURPOSE:To prevent the data error of memory read output data signal from being generated by the miss of read timing signals. CONSTITUTION:This device is provided with a parallel/serial converting part 4 to convert memory parallel data 110 read from a memory 2 to serial data and to output them as output data signals 102, read timing shift circuit 13 to supply a read timing signal 115 to this parallel/serial converting part 4, read timing signal selecting part 11 to supply a read timing signal 114 to the read timing shift circuit 13 or the like, and the read timing shift circuit 13 outputs the read timing signal 1-15 complementing the missed signal of the read timing signal 114 with a signal delayed for 8 bits.</p> |
