| 摘要 |
PURPOSE:To easily and successively extract any arbitrary channel even in the case of multiple interleaved data sequences. CONSTITUTION:A storage part 11 is provided with parallel (n) pieces of memory cells having (m) bits in the depth, succesisvely shifts multiple data sequences D11 with a signal S12 as an address and transmits the (n) sequences of outputs di-dn. An address counter 12 repeatedly counts clocks S11 supplied from the outside from '1' to 'm' and generates the signal S12. A comparator part 12 compares reference patterns P1-pn supplied from the outside with the output data d1-dn and transmits a frame synchronizing signal S13 when they are coincident. When the frame synchronizing signal S13 is received, a multiple synchronizing counter 14 counts the clocks S11 while setting the counter to the designated value of an extracting channel designating signal S14 supplied from the outside and transmits a data extraction timing signal S15 in the cycle of (m) bits. Corresponding to the data extraction timing signal S15, a flip-flop 15 samples the output d1. |
