| 摘要 |
PURPOSE:To prevent normal phase error corresponding to frequency off-set by outputting signals at a frequency corresponding to the output of an adder, which adds outputs of a counter and a register, from a voltage controlled oscillation circuit. CONSTITUTION:This loop is provided with a random walk filter 3 to selectively output up pulses and down pulses corresponding to the output of a phase frequency comparator 2, and counter 4 to a cumulate pulses outputted from this filter 3. Further, the loop filter is constituted by providing a register 5 to output any specified value corresponding to the output of the phase comparator 2 and an adder 6 to add the outputs of the counter 4 and the register 5. On the other hand, a voltage controlled oscillation circuit 7 outputs the signals at the frequency corresponding to the output of the adder 6. Namely, this is the second-order phase locked loop provided with the loop filter, the characteristic of the loop is decided by the characteristic frequency and attenuation factor of the phase locked loop, and these characteristic frequency and attenuation factor are decided by the gain of the voltage controlled oscillation circuit and the value outputted by the register or the like. |
