| 摘要 |
PURPOSE:To normally operate even in a faster clock period when shift registers such as 4-bit shift registers are connected in series by suppressing a delay time of data in the register. CONSTITUTION:3-input NOR gates 21, 22 are used, and gates until input data are output are formed of four 2-input NOR circuits and two 3-input NOR circuits. Accordingly, a delay time of data in a shift register can be suppressed as compared with a normal shift register, and when shift registers such as 4-bit shift registers, etc., are connected in series, a normal operation can be executed even in a faster clock period. |
