发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To reduce the frequency fluctuation of an output signal compared with a normal state when the input signal of the phase locked loop circuit is instantaneously interrupted or the phase is changed. CONSTITUTION:The phase locked loop circuit provided with a voltage control oscillator 1 to output an output signal (b) which phase is locked to an input signal (a), frequency divider 2 to frequency divide the output signal (b), phase comparator 3 to detect phase difference between the output of the frequency divider 2 and the input signal (a) and low-pass filter 4 to smooth the output of the phase comparator 3 is equipped with diodes 5 and 6 for limiting the output voltage of the low-pass filter 4, resistors 7 and 10, capacitor 8 and buffer 9, the output voltage amplitude value of the low-pass filter 4 is limited, and the frequency fluctuation is reduced.
申请公布号 JPH05284015(A) 申请公布日期 1993.10.29
申请号 JP19920074981 申请日期 1992.03.31
申请人 发明人
分类号 H03L7/093 主分类号 H03L7/093
代理机构 代理人
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