发明名称 DATA PROCESSOR
摘要 PURPOSE:To more flexibly set up the sampling frequency of an A/D converter through software control by allowing a system body circuit to periodically accessing data outputted from the A/D converter by its own timing control. CONSTITUTION:When the system body circuit 1 accesses a control circuit 2 in order to obtain digital data, the circuit 2 decodes address data passed through an address bus 5 by its inner decoder circuit 22 and inputs the decoded data to the A/D converter 3 as a sample start signal. The access to the circuit 2 is controlled by software incorporated in the body 1 and periodically executed to set up sampling frequency. Namely, the sampling of the A/D converter 3 is started synchronously with access to data outputted from the converter 3 and the sampling frequency is set up by controlling the access so as to periodically access the data by the software incorporated in the circuit 1.
申请公布号 JPH05282101(A) 申请公布日期 1993.10.29
申请号 JP19920082066 申请日期 1992.04.03
申请人 发明人
分类号 G06F3/05;G10H7/00;G10L11/00;G10L15/28;H03H17/02;H03M1/12 主分类号 G06F3/05
代理机构 代理人
主权项
地址