发明名称 DECENTRALIZED ALTERNATION SYSTEM FOR ASYCHRONOUS TRANSFER MODE
摘要 <p>PURPOSE:To assure the sequence properties of cells despite a decentralized alternation and to absorb the traffic fluctuation by referring to some of identified bits of a virtual channel of a cell header and performing the control of the cells based on the combination of those bits. CONSTITUTION:A controller 82 detects the overload of a virtual path VP and this detection information is sent to a centralized monitoring device 61. Then a specific VP of decentralization is decided based on the VP having the overload and the data on the common stand-by capacity, and the updating information is sent to the controller 82. The controller 82 updates the fields 87-89 of a VIP conversion field 83 and sets the address flag of a field 90 at '1'. Then a virtual path identification number 2 is read out of the header of a cell 96 and the in-VPI of a field 84 is searched out of a VIP conversion table 83 corresponding to a transmission line 91. An access is given to the address of a VPI number 2. Then the controller 82 reads out the out-transmission line number and an out-VIP number of the corresponding field in accordance with '0' and '1' of a lower bit of a virtual channel identification VCI. There read-out numbers are sent back to a switch 81.</p>
申请公布号 JPH05284174(A) 申请公布日期 1993.10.29
申请号 JP19920082584 申请日期 1992.04.06
申请人 发明人
分类号 H04L12/28;H04L12/56;(IPC1-7):H04L12/48 主分类号 H04L12/28
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