| 摘要 |
PURPOSE:To increase operational clock frequency of the final stage without changing the operational clock frequency of the DTO itself. CONSTITUTION:The output (control voltage) of a latch circuit 120 prepares the first saw tooth wave data to be outputted from the DTO consisting of an adder 130, and a latch circuit 140. The control voltage is halved by a coefficient unit 150 and added to the first saw tooth wave data in an adder 160, making the second saw tooth wave data with the phase deviated from the first saw tooth wave. The first and second saw tooth waves are used as the phase input data of sine function ROMs 170 and 200, making the sine wave digital data of deviated phase, which are alternately selected by a selection circuit 220, making the sine wave output of the clock frequency rate doubling the frequency prepared by the DTO. |
