| 摘要 |
PURPOSE:To realize a small sized and high speed PLA by generating automatically a clock starting the operation of an OR logical section in an optimum time through a dummy circuit similar to an AND logical section in matching with the end of logical operation of the AND logic. CONSTITUTION:The programmable logic array (PLA) of this invention has the dummy logical circuit similar to the AND logical section in addition to the AND logical section and the OR logical section. Then the AND logic is started by a clock phi1, a phi2 generated automatically through the dummy logical circuit starts the OR logic the same time as the end of this logic and the entire PAL operation is finished. That is, the logical processing time of the PLA is from the leading of the phi1 at a time t1 until the voltage decision of output terminals O1, O2 at a time t5, the logical operation is executed continuously and a high speed logical processing time is attained by a single phase clock phi1. |
