发明名称 VOLTAGE REDUCTION CIRCUIT
摘要 <p>A circuit for reducing a voltage received at an input (3) of the circuit to provide a lower output voltage at an output (5) of the circuit comprises a voltage stabilizer (Zener diode ZD1 and the base-emitter junction of a transistor T2) connected between a point at a reference potential (ground or earth point) and the output (5) for stabilizing the output voltage at a predetermined level VZD1+VbeTR2, resistors (R1, R2) between the input and the output, and switch means (T1, T3, R3 to R6) responsive to the output voltage and arranged to coact with the resistors to provide a reduced resistance R1 between the input and output when the output voltage falls below the predetermined level, e.g. as a result of the input voltage falling or the output current rising. When the output voltage is above the predetermined level, T2 is turned on, and T3 and T1 are turned off; if the output voltage falls below the predetermined level, T2 turns off and T3 and T1 turn on, thereby effectively shorting out the resistor R2. As shown, the circuit forms part of an a.c. energised power supply suitable for use with a circuit which needs to remain operational even when the principal supply voltage varies between wide limits, for example a residual current device operable even when the mains voltage is as low as 50 volts a.c.</p>
申请公布号 WO1993021573(A1) 申请公布日期 1993.10.28
申请号 GB1993000834 申请日期 1993.04.21
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