| 摘要 |
A semiconductor memory device is subjected to a test operation, before delivery from the factory, for screening defective products. The device is placed in a diagnostic mode for carrying out the test operation on the signal circuits (23 to 32) when a discriminator (33) produces an internal control signal (EBL) for the test operation. The data and power signals (CS/ WE/ A1 to Ax/ A1 to Ay) supplied to the device pins have active levels within a predetermined voltage range. The discriminator is responsive to a test signal (TS) received at a test pin and is activated at a level which lies outside the predetermined voltage range. Thus the semiconductor memory device does not mistakenly enter the diagnostic mode after being assembled in an electronic system. <IMAGE> |
