Method and apparatus for implementing a priority adjustment of an interrupt in a data processor

摘要

An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt signal which either indicates that the interrupt priority has been adjusted or identifies a highest prioritized interrupt request when no adjustment in priority is made. A first logic circuit functions to receive a priority adjust request signal and compares the adjust signal with one or more interrupt signals to determine if an adjustment is required. A second logic circuit functions to identify the highest prioritized interrupt request of a plurality of interrupt requests and provides the encoded interrupt signal in response thereto. In one form, the encoded interrupt signal is translated into a value for use in a software exception processing routine within the CPU. The software exception processing routine can perform a variety of user specified functions with the encoded adjusted priority interrupt signal.