发明名称 |
Column redundancy architecture for a read/write memory |
摘要 |
An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of fuses for storing the column address responsive to which its associated redundant column is to be selected. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column. |
申请公布号 |
US5257229(A) |
申请公布日期 |
1993.10.26 |
申请号 |
US19920830314 |
申请日期 |
1992.01.31 |
申请人 |
SGS-THOMSON MICROELECTRONICS, INC. |
发明人 |
MCCLURE, DAVID C.;IYENGAR, NARASIMHAN |
分类号 |
G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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