发明名称 |
Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell |
摘要 |
A method for forming a transistor and a capacitor to provide, in one form, a DRAM cell (10). The capacitor of cell (10) is formed within a substrate (12). The capacitor has a first capacitor electrode (16) and a second capacitor electrode (20). A dielectric layer (18) is formed as an inter-electrode capacitor dielectric. A first transistor current electrode (36) is formed overlying and electrically connected to the first capacitor electrode (16). A channel region (38) is formed overlying the first transistor current electrode (36). A second transistor current electrode (40) is formed overlying the channel region (38). A conductive layer (30) is formed laterally adjacent the channel region (38) and isolated from the substrate (12) by dielectric layers (22 and 28). A conductive layer (30) functions as a gate electrode for the transistor and a sidewall dielectric (34) functions as a gate dielectric.
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申请公布号 |
US5256588(A) |
申请公布日期 |
1993.10.26 |
申请号 |
US19920856411 |
申请日期 |
1992.03.23 |
申请人 |
MOTOROLA, INC. |
发明人 |
WITEK, KEITH E.;MAZURE, CARLOS A.;FITCH, JON T. |
分类号 |
H01L27/04;H01L21/822;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):H01L21/70;H01L27/00 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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