发明名称 A CHANNEL SCANNING AND PRIORITY CHANNEL MONITORING CIRCUIT FOR A RADIO RECEIVER
摘要 1314577 Tuning radio receivers; pulse generators; multistable state and muting circuits MOTOROLA Inc 31 July 1970 [8 Aug 1969] 37134/70 Headings H3Q and H3T In a superhet receiver for receiving a number of different channels, one of the channels is a priority channel which is received at all times during which a signal is transmitted on it and which is continually sampled during the reception of signals on other channels and which is locked on to whenever a carrier is detected during the sampling interval. The receiver has a mixer 12 to provide reception on different channels and an oscillator 13, 14 connected to the mixer 12 for providing output signals at different frequencies corresponding to the different channels and a channel scanning and priority channel monitoring circuit is provided comprising switching means 34, 35 having at least a first and a second operating condition coupled to the oscillator for controlling the oscillator output frequency, a pulse generator 58, 68 and/or 43, 44 for applying pulses to the switching means 34, 35 and detecting means 21, 80 for detecting the presence of a received signal on a channel for inhibiting the application of pulses from the pulse generator to the switching means in consequence of the received channel being on the priority channel. A bistable circuit 34, 35 is switched from one of its states to its other state cyclically by clock pulses from a free-running generator 43, 44 via transistor 50 and diodes 54, 55. Also assuming transistor 34 is off and transistor 35 is on, transistors 30, 37 and 38 are on to switch in oscillator 13 and light lamp 39 to indicate that the priorty channel is being monitored. A negative pulse at the collector of 35 reverse biases diode 57 and cuts off transistor 58. This transistor acts like a monostable circuit as when the charge on capacitor 59 has reduced sufficiently transistor 58 again conducts and the output pulse via diode 62 turns transistor 35 off and transistor 34 on. This switches transistor 31 on and transistors 30, 37, 38 off so that the oscillator 14 corresponding to the other channel is switched in. Similarly the transistor 68 acts as a monostable to switch the state of the bistable back so that transistor 34 is off and transistor 35 is on. The monostable transistors 58, 68 function as a clock pulse generator cyclically changing the state of the bi-stable circuit 34, 35 and operate at a frequency higher than that from the clock pulse generator 43, 44. With no signal carrier detected but noise present the output repetition rate from the frequency-sensitive squelch circuit 80 is high so that noise level storage capacitor 87 is discharged to hold transistor 94 on and provide a squelch output potential near zero on line 101. The output enables the bi-stable to function as above to scan the channels and also this output is passed by 105 to open the audio switch 22 so that no audio signals pass to the speaker 26. When a carrier is detected a few or no pulses are passed by the squelch circuit 80, capacitor 87 charges and transistor 94 is made non-conductive. The positive output on line 101 inhibits monostable operation of the transistors 58, 68 which are made conductive. Also the output on 101 is applied via diode 111 to the junction of diode 52 and capacitor 53 so as to inhibit clock pulses from being applied from the generator 41 to the bi-stable circuit 34, 35 so that the bi-stable is stopped in the state in which the carrier was detected. The positive potential on 105 closes audio switch 22 to allow audio output of the detected channel. If the carrier detected corresponds to the non-priority channel transistor 34 is on and transistor 35 is off so that transistor 115 is conductive to allow diode 52 to pass a clock pulse from generator 41 to change the state of the bi-stable 34, 35 to transistor 34 off and transistor 35 on so as to monitor the priority channel. Transistor 115 then turns off and if the priority channel is present the output of the differential amplifier 92 continues to inhibit further clock pulses from 58, 68 and 41 until the carrier ceases. The sensitivity of the squelch circuit is decreased when the priority channel is monitored by the connection from the collector of transistor 34 via resistor 120 to the base of 94 so that capacitor 87 must charge to a higher voltage for detection of a carrier on the priority channel. This avoids errors in locking on to unwanted signals, e.g. due to noise. Muting of the audio output when a new channel is being sampled and to provide a delay in unmuting of the audio output to allow for a new channel oscillator 13 or 14 to start is provided by switch 23. Transistor 125 is normally non-conductive but conducts to shunt the audio output when either of the monostable delay transistors 58 or 68 is non-conductive during sampling. The delay in unmuting is provided by the delay transistors 58 or 68 when a carrier is detected. A transistor 128 is controlled by the bi-stable 34, 35 so that when a non-priority channel is received transistor 128 is conductive to insert a resistor 127 across the audio output so as to reduce the output signal level. When a priority channel is received transistor 128 is off and the audio output is increased. In order to prevent a dim or flickering output from the lamp 39 when the bi-stable 34, 35 is scanning between priority and non-priority channels transistors 137, 138 render transistor 38 non-conductive during the delay time when transistor 58 is non-conductive so that the lamp 39 is only energized for steady state monitoring of the priority channel. The generator 41 may be a unijunction transistor or an S.C.R. relation oscillator and indicator lamps 39 may be provided for both channels. When the transmit mode switch is pushed transistors 131-135 are made conductive so as to prevent bi-stable transistors 34, 35 from conducting. In a modification (Fig. 2, not shown), for scanning four channels determined by oscillators (170-173) the output from bi-stable transistor 34 is fed to (150) bi-stable circuits (155, 156) which are similar to 34 and 35 and are connected as a two-stage binary counter. The outputs from the counter sequentially control transistor switches (160-163) so as to cyclically connect the oscillators (170-173) corresponding to the four channels in circuit with the receiver. A transistor (181) feeds priority select switch (180) and the transistor (181) is non-conductive whenever ground potential is applied from transistor 34 when a non-priority channel is detected. When a carrier is detected a positive potential from transistor 94 is applied via (185) to inhibit further pulses from the transistor 34 being supplied to the counter (155, 156) the operation beng similiar to that of Fig. 1.
申请公布号 ZA7005182(B) 申请公布日期 1971.04.28
申请号 ZA19700005182 申请日期 1970.07.27
申请人 MOTOROLA INC 发明人 CHAMMAN R;MOORE G
分类号 H04B1/40;H03J5/24;H03J7/18;H03J7/20;H04B1/16 主分类号 H04B1/40
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