| 摘要 |
PURPOSE:To set a delay in channel data for each time slot in a time switch circuit having a memory by 2-frames. CONSTITUTION:Channel data by one frame are stored alternately two channel memories 1, 2 for each frame by using AND gates 8, 9. A control memory 3 receives and stores read address information and control information of the channel memories 1, 2. A timing generating circuit 4 generates a write address of the channel memories 1, 2 and a read address of the control memory 3 synchronously with a channel data input 6. A selection circuit 5 selects which of data outputted from the two channel memories 1, 2 is to be selected based on a selection signal generated by the timing generating circuit 4 and the control information stored in the control memory 3 and the selected channel data are outputted from the circuit 5 externally as channel data. |
