发明名称 MULTILAYER WIRING FORMING METHOD
摘要 PURPOSE:To avoid the removal of a cap metal layer of a lower wiring layer during the connecting hole etching away step within the multilayer wiring forming step. CONSTITUTION:A lower wiring layer 14 is formed on an insulating film 12 covering a semiconductor substrate 10. Within the wiring layer 14 comprising a barrier metal layer such as WSi2, etc., an Al or Al alloy layer and a cap metal layer 14c such as WSi2, etc., are successively laminated upward, the cap metal layer 14c contains a conductive material such as Al, etc., using ion implanting step etc. After covering the whole surface with the wiring layer 14 and forming an insulating film 18, a connecting hole 18A is formed in the insulating film 18 by dry-etching step using a resist layer 20 as a mask as well as fluorine base gas e.g. CHF3, etc., as an etching gas. Through these procedures, a fluoride such as Al fluoride (AlF3), etc., can be produced so as to suppress the etching away step of the cap metal layer 14c.
申请公布号 JPH05275541(A) 申请公布日期 1993.10.22
申请号 JP19920102307 申请日期 1992.03.28
申请人 发明人
分类号 H01L21/302;H01L21/28;H01L21/3065;H01L21/3205;H01L21/768;H01L23/52;H01L29/43;(IPC1-7):H01L21/90;H01L21/320;H01L29/46 主分类号 H01L21/302
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