| 摘要 |
<p>PURPOSE:To reduce the circuit scale of a programmable timing signal generating circuit. CONSTITUTION:A 19-bit base register 21 and an 8-bit offset register 22 which are controlled by a CPU 6 are provided. An adder circuit 20 which calculates the sum of their outputs Ba and Bb is provided, and timing data B is generated. Thus, the function performance is maintained and the circuit scale is reduced because a large-scale register group for timing data can be substituted.</p> |
