| 摘要 |
<p>PURPOSE:To improve the use efficiency of a ROM and shorten the execution time of a program by controlling the input and output of data directly through a dedicated read control signal line. CONSTITUTION:In a 1st cycle, a CPU 1 outputs the value of an internal program counter to an address bus 6 to hold a read/write control signal at level H. Once this signal is set to H, an operation code is read out of the ROM 2 and the CPU 1 detects the operation code and decodes an instruction to perform a specified process by the operation code in the following cycle. The dedicated read control signal of the dedicated read control signal line 9 is set at L here, so an input/output port 5 does not output input data to a data bus 6. In a 2nd cycle, the CPU 1 holds the read control signal of the input/output port 5 at H, outputs the input data from the input/output port 5 to the data bus 6, and specifies the read/write control signal at L, thereby writing the input data from the input/output port in a RAM 3 address.</p> |
