| 摘要 |
PURPOSE:To obtain a programmable delay element with a wide adjustment range of a delay time and providing a stable delay time with respect to the digital variable delay circuit used for delay adjustment processing of various digital signals. CONSTITUTION:A signal frequency multiplier means 12 generates a signal whose phase is in phase with a reference signal and whose frequency is multiplied by an integral number of multiple with respect to the reference signal. A counter means 14 uses the signal generated by the signal frequency multiplier means 12 as a count clock signal and counts a designated number of delay data input. A state storage control means 16 has a circuit storing an output state and the state is transited by a count end signal of the counter means 14. Thus, the delay time equivalent to the count by the counter means 14 is given to a digital input signal inputted to the signal frequency multiplier means 12. |
