| 摘要 |
<p>PURPOSE:To attain the minimum wait insertion for preventing the reverse of the time relation of a memory control signal and access data such as an address or data in a memory access without necessitating the entire rewriting of a software or the design change of a hardware. CONSTITUTION:This device is equipped with an address register 13 which stores the access data, comparator 15 which compares the storage value of the address register 13 with a bus data value, and bus cycle generator 12 which extends a bus cycle by a comparison signal CS from the comparator 15.</p> |
