发明名称 LOGIC SIMULATION METHOD
摘要 PURPOSE:To improve the extraction rate of logic defects before actual machine adjustment by setting contention operation test circumstances in the test program preprocessing stage on the master instruction processor side and gathering data of tested memories to discriminate the test result in the post-processing stage. CONSTITUTION:A test program preprocessing part 101 on the master instruction processor side sets the contention operation test circumstances and sets data of storage devices or various cache memories required for test parts 102 and 103. In test program test parts 102 and 103, both of the master instruction processor and a sub-instruction processor issue test instructions to perform the contention operation test of storage devices and various cache memories. A test program postprocessing part 104 gathers data of storage devices or various cache memories tested by test parts 102 and 103 and discriminates the test result.
申请公布号 JPH05265793(A) 申请公布日期 1993.10.15
申请号 JP19920063489 申请日期 1992.03.19
申请人 发明人
分类号 G06F11/22;G06F11/26;G06F17/50 主分类号 G06F11/22
代理机构 代理人
主权项
地址