发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To provide an arithmetic unit provided with a shift circuit having the high availability by combining the shift circuit and a buffer register, and providing a bus selecting function using the data format-converting function and the shift function. and the function which designates a path for application of the buffer register as a temporary register or the like. CONSTITUTION:This arithmetic unit is provided with a computing part which carries out various types of operations and an internal bus BUSi, to which an operational register, etc., are connected. And the unit is provided with buffer registers AXR1 and AXR2 to perform the selective transfer of data of the external buses ABUS and BBUS to which the arithmetic unit is connected, and a shift circuit BSF to select the data given from the registers AXR1 and AXR2 or the bus BUSi and to shift the input data by a prescribed number of bits in the prescribed direction to selectively output these data to the registers AXR1 and AXR2 or the bus BUSi.
申请公布号 JPH05265750(A) 申请公布日期 1993.10.15
申请号 JP19920064147 申请日期 1992.03.19
申请人 发明人
分类号 G06F7/00;G06F5/01;G06F7/76;G06F9/315 主分类号 G06F7/00
代理机构 代理人
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