发明名称 DIGITAL PLL DEVICE
摘要 PURPOSE:To provide the digital PLL device having good accuracy in arithmetic operation even when the low-order bit is cut down in an integrating device. CONSTITUTION:The digital PLL device consists of a phase comparison section 1 comparing the phase difference of a digital input signal, digital voltage control oscillator 4, and loop filter 2. The digital voltage control oscillator 4 is of an integrating device made up of an entire adder 7, to which high-order (k) bits of (n) bit outputted by the loop filter 2 are inputted and the code bit of (n)-bit digital signal is inputted to a carry input terminal.
申请公布号 JPH05268076(A) 申请公布日期 1993.10.15
申请号 JP19920093759 申请日期 1992.03.19
申请人 发明人
分类号 G06F7/38;H03L7/06;H03L7/099 主分类号 G06F7/38
代理机构 代理人
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