| 摘要 |
<p>PURPOSE:To provide the circuit enabling the software program processing while combining the syntax processing related to the encoding and decoding processing and its semantic processing. CONSTITUTION:In a fixed length decoding instruction, the bit string of an input FIFO 121 is transferred to an unpacked shifter 122. The shifted data is sent to a temporary register 124, which is adjusted by a right-adjust shifter 111 and transmitted to a pipeline register 104. In a variable length decoding instruction, the operand value and the output of the unpacked shifter 122 are supplied to a table address generation section 141, making the generation address the execution start address for variable length decoding processing. In the fixed length encoding instruction, the data of a pipeline register 106 is adjusted by a left-adjust shifter 112 and sent to a temporary register 134. The part of data is updated in a back shifter 132, packaged in an output FIFO 131. In the variable length encoding instruction, the operand value and the data of the register file 102 are added so as to make a variable length encoding table address.</p> |
