| 摘要 |
<p>PURPOSE:To reduce the circuit scale by inputting a signal to a discrete cosine transformation(DCT) and an inverse DCT storage means, shifting and adding the value read from the storage means in matching with a bit number of the input value. CONSTITUTION:A DCT input value is inputted to shift registers 160-167 in the forward DCT operation and addition or subtraction is implemented between two terms by 1-bit serial adders 170-177 from the LSB side, the result is inputted to ROM accumulators 180-187, and the result is subjected to repetitive shift addition and the result of DCT is obtained. On the other hand, in the case of inverse DCT, the inverse DCT input value is inputted to the shift registers 160-167 and inputted directly to the ROM accumulators 180-187, then a switch 203 of the adders 170 177 is set to the position of the inverse DCT from the LSB side to bypass the addition. Furthermore, coefficient ROMs in the accumulators 180-187 are set to the position of the inverse DCT and the content of the ROMs is switched. Registers 190-197 are divided into two, two terms for addition/subtraction are inputted to an adder 200 and the result of 2-terms inverse DCT is obtained by addition/subtraction.</p> |
