| 摘要 |
PURPOSE:To correctly keep the count value of a frame counter. CONSTITUTION:A first counter 20 is reset in response to BIC and outputs a first block synchronizing signal when the block of input data is synchronized. The second counter 24 is reset by the first synchronizing signal or the second block synchronizing signal which is generated by a timing signal generating circuit 26 based on its own output and also is stepped by a clock signal like the first counter 20. When the count value of the second counter 24 is in the first half part of a whole block count number, only the second block synchronizing signal is given to the frame counter 32. When it is in the latter half part, the first and second block synchronizing signals are respectively given to the count signals of the frame counter 32. |
