| 摘要 |
PURPOSE:To realize a high delay time resolution by utilizing a difference in a delay time when a signal is inputted to each level input terminal of a series gate circuit. CONSTITUTION:A delayed signal IN passing through either AND circuit depending on logic of a selection signal S is fed to a 1st level input terminal or a 2nd level input terminal of an OR circuit 10, and outputted to a terminal 15 from an output terminal of the circuit 10. Since the signal input from the 2nd level input terminal gives a larger delay time than that from the 1st level input terminal in the circuit 10 of series gate configuration, the delay time is varied by digital control by controlling the input terminal for the signal IN in the circuit 10 through the changeover of a signal S and a high delay time resolution is realized. |
