| 摘要 |
PURPOSE:To provide a data memory bank access system capable of speeding up a processing when the signal processor has the two arrangements of two operand inputs. CONSTITUTION:In this signal processor, an arithmetic part 101 shows a logical arithmetic circuit and a multiplication circuit, etc. First and second general-purpose registers 102 and 103 are used as registers for inputting operands to the arithmetic part 101 and as registers for saving/preserving data. A data memory 104 is provided with plural data memory banks. A sub bus 105 is provided with a bus multiplexer 108 to select which one of these sub buses 105 is connected to an internal data bus X106 and an internal data bus Y 107. Therefore, the bank storing the data of two operands can be connected to the sub bus 105 corresponding to the processing, and two operands can be simultaneously accessed in any case. |
