| 摘要 |
PURPOSE:To make an output stable even at the time of changing-over and to make a circuit scale small concerning a clock change-over circuit executing change-over to a clock which is delayed more than 0 deg. as against the clock before change-over and also is delayed by time which is shorter than time when respective clock signals are being an effective level during one cycle between the two clocks having a same duty ratio. CONSTITUTION:The circuit is constituted of a clock gate means 1 which detects a timing when the both two clock signals are an ineffective level, a delay means 2 which makes a control signal delay so as to change-over the clocks at the first, at least, timing after the control signal for commanding the change-over of the clocks is changed-over at first and a selecting means 3 which is changed- over by the delayed control signal. |
