发明名称 TIME CONSTANT CIRCUIT
摘要 PURPOSE:To reduce tertiary higher harmonic distortion in an output signal by providing a buffer amplifying circuit for outputting a level detecting signal and driving a time constant setting circuit, and also, allowing an input signal of the time constant setting circuit to be subjected to negative feedback to an input side. CONSTITUTION:A level detecting signal D being a full-wave rectifying current being proportional to a level of an input signal from a level detecting circuit 4 is impressed to a positive input of an operational amplifier A61 of a buffer amplifier 61. A (b) point of an emitter side of a transistor Q61 is connected to an inversion input of the operational amplifier A61, therefore, a negative feedback circuit of the operational amplifier A61 is constituted. Accordingly, by this negative feedback operation, a variation portion of a base-emitter voltage caused by a variation of an emitter current of the transistor Q61 at the time of charging of a capacitor C61 is absorbed. As a result, a condition that a peak position of a voltage of an (a) point and a peak position of a voltage of the (b) point are always equal to each other is held, therefore, a faithful level control is executed to the level of the input signal.
申请公布号 JPH05267965(A) 申请公布日期 1993.10.15
申请号 JP19920061631 申请日期 1992.03.18
申请人 发明人
分类号 H03G7/08 主分类号 H03G7/08
代理机构 代理人
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