| 摘要 |
PURPOSE:To enable highly efficient data transmission to be executed by extending only a required information signal so as to take it out from transmission digital data including a synchronizing signal through the use of an independent clock which is asynchronized with the data. CONSTITUTION:Since the eight bits of the information signals are respectively outputted by following the synchronizing signal, 32 inputs C1 are concerned within the 64 inputs, for example, of a coinciding circuit 4 in order to extract the information signal in a parallel input. Data to be inputted to a gate circuit are C2, C6, C10...C30 within the inputs because the median of the 8th bit of the information signal is counted by a counter circuit through the use of the second input of respective four input terminals. The parallel input is adopted as the respective D inputs of D-shape FF and a counter output signal which is outputted from the counter circuit 5 is used for a clock. Then, only required information is extended and taken-out in parallel. Thus, this is more effective than adding a preamble signal to transmission data and providing DPLL at a reception side. |
