METHOD AND STRUCTURE FOR SUPPRESSING CHARGE LOSS IN EEPROMs/EPROMs AND INSTABILITIES IN SRAM LOAD RESISTORS

摘要

Suppression of charge loss and hot carrier degradation in EEPROMs and EPROMs, and of instability in the polysilicon pull-up resistors (R1, R2, 14) associated with SRAMs is achieved by the inclusion of at least one layer of silicon-enriched oxide (26, 28, 30) in the MOS structure. In such MOS structures, the silicon-enriched oxide layer (26, 28, 30) may be disposed immediately beneath the interlayer dielectric layer (16), or immediately beneath the inter-metal oxide layer (20), or immediately beneath the passivation layer (24), or in any combination of these locations. Each silicon-enriched oxide layer (26, 28, 30) has a refractive index of at least about 1.50, and preferably contains at least about 10<17> per cm<3> dangling bonds.