CCD delay line.

摘要

A CCD delay line. First, second and third transfer regions are formed in semiconductor substrate. Output portions of the second and third transfer regions are connected to a differential amplifier. The output terminal of the differential amplifier is connected to input sources of the first and second transfer regions. The third transfer region is able to carry at most 30% of maximum amount of charge which the first and second transfer regions can carry. A signal is supplied from a signal source through a clamp circuit to an input gate electrode of the first transfer region. Bias changing means independently change one of an input bias voltage supplied to the input gate electrode of the first transfer region and a reference bias voltage supplied to an input gate electrode of the second transfer region. <IMAGE>