| 摘要 |
<p>The invention describes a system with at least two complementary transistors, with n and p channels, but including a heterostructure between III-V materials. In order to balance the threshold voltages in the two channels n (2 DEG) and p (2 GHG), at least two doping planes, namely as p doping plane (19) and an n doping plane (20) are included in two layers of the heterostructure, at levels included between the channels (2 DEG, 2 DHG), and the gate electrodes (7, 8). The n doping plane (20) is later removed by localised etching plumb with the p channel transistor. Application to fast logic. <IMAGE></p> |
