发明名称
摘要 PURPOSE:To execute easily a logic test by connecting a prescribed test section with an AND array forming a programmable logic array. CONSTITUTION:Switching MOSFETs Q (Q1-Q'm) are provided while being connected to each product term line P (P1-P'm), and a test wire It prolonged to the product term lines P while intersecting orthogonally with them is provided. Further, a storage element Mt is provided at a cross point between the product term lines P and the test line It. Consequently the test section C is formed by them. Each FET Q is subjected to ON-OFF control selectively by a control line D (D1,D2). In conducting the logic test, input lines I (I1-In) are all brought into a low level, a test signal is fed to the test line It and the FETs Q are controlled selectively. Thus, the logic test is executed easily.
申请公布号 JPH0573088(B2) 申请公布日期 1993.10.13
申请号 JP19840273869 申请日期 1984.12.27
申请人 RICOH KK 发明人 FUJII KOICHI;TAKADA AKIRA;OKA ZENJI
分类号 H03K19/177;G01R31/3185;(IPC1-7):H03K19/177 主分类号 H03K19/177
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