| 摘要 |
A BICMOS NAND gate (40) has a CMOS NAND gate (41), a bipolar pull-up transistor (47), a bipolar pull-down transistor (48), series connected N-channel transistors (43-45) coupled between the base and collector of pull-down transistor (48), N-channel transistors (42, 46, 49, and 50), and a VBG generated reference voltage (51). N-channel transistor (46) receives a variable bias voltage provided by transistors 49, 50, and VBG generated reference voltage (51). At high power supply voltages, N-channel transistor (46) prevents pull-down transistor (48) from becoming saturated when BICMOS NAND gate (40) is operating at high frequency, when an input becomes skewed, or a glitch develops, yet allows for satisfactory operation BICMOS NAND gate (40) at low power supply voltages.
|
