发明名称 Circuit arrangement for mitigating power switch capacitance
摘要 A circuit arrangement is provided to mitigate the parasitic capacitance that typically is associated with solid state switches which are designed to carry high current magnitudes. By disposing a capacitive component in series with a power switch which, in turn, is connected in series with an inductive component, the overall capacitance of the switch and capacitive component are significantly reduced. In a preferred embodiment of the present invention, the capacitive component is a diode with a voltage potential provided at the cathode of the diode so that the parasitic capacitance of the diode can be varied to tune the total circuit for the purpose of achieving a specific resonant frequency. In applications where high frequency signals are injected into the circuit for purposes of measuring a parameter, such as rotor position, the present invention is beneficial because of the ability to tune the frequency resulting from the residence of the series LC circuit which comprises a conductive component, such as a motor stator winding, and a capacitive component, such as a power switch which possesses an inherent parasitic capacitance. Another benefit of the present invention is the fact that it makes possible the use of smaller components in a snubber network associated with the inductive component because of the increase in resonant frequency achieved by the decrease in capacitance of the series LC circuit.
申请公布号 US5252907(A) 申请公布日期 1993.10.12
申请号 US19920870852 申请日期 1992.04.20
申请人 HONEYWELL, INC. 发明人 HARRIS, WILLIAM A.;PEARMAN, ARTHUR N. J.
分类号 H02P29/02;H02P25/08;H03K17/16;H03K17/695;(IPC1-7):H02P5/40;G05F1/40;H03K3/26 主分类号 H02P29/02
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