Semiconductor memory used for changing sequence of data

摘要

An SRAM adapted for changing the sequence of data. A counter 7 generates a sequentially increasing address signal. A write designation circuit 2a sequentially designates a memory cell row to be selected for writing in response to the address signal. Conversely, a read designation circuit 3a designates a memory cell row in response to the address signal in a sequence determined by a predetermined rule. The generation of an address signal, which changes in a complicated manner and is required for changing the sequence of data, is not required, so that the amount of the operation process by the CPU is decreased.