| 摘要 |
PURPOSE:To eliminate the position uncertainty generated at the time of test on the reception equipment side by providing a rearranging circuit of bit position of a parallel signal and an PN system synchronizing circuit and monitoring the output signal string of the rearrangement circuit, thereby maintaining the present selective pattern at the time of coincidence between the output signal train and a specific PN code system. CONSTITUTION:Parallel signals P1 to P4 for test are inputted to a parallel/serial converter 1 as a test jig and are outputted as a serial signal. The serial signal demodulated by a MODEM 2 as the test object is converted to original parallel signals and is inputted to the rearrangement circuit 41 of a phase uncertainty eliminating circuit 4. A PN synchronizing circuit 42 monitors the bit P1 of the circuit 41, and another bit arrangement pattern is selected by the circuit 41 when it does not coincide with PN1 of a specific pattern, but the circuit 41 keeps the preset selective pattern when it coincides with PN1. Thus, the phase uncertainty due to serial/parallel conversion at the time of test in the communication system performing the multivalue conversion is eliminated on a reception side. |
